1. Field of the Invention
The present invention relates to a method for testing a memory device, and more particularly to a method for testing a memory device with a long-term clock signal by automatically performing a precharge only after activation.
2. Description of the Prior Art
As generally known in the art, memory devices are subjected to stringent tests under particular conditions before being released as end products. One of such tests is a burn-in test performed on memory devices in a wafer level under more severe conditions than those which will actually be applied to the devices. The burn-in test applies a higher voltage at a higher temperature to detect any flaw in memory chips before being supplied to end-users and thereby ensure reliability and productivity of memory devices.
The burn-in test on memory devices is performed using a burn-in system. As the operation frequency of memory devices increases, new burn-in systems need to be purchased to test the devices in the prior art, thereby resulting in the increase of expenses for testing.
In order to solve this cost problem, in the prior art, memory devices operating at a high frequency have been tested using a system operating at a low frequency. Such a test generally requires a test mode of a long-term clock (a low-frequency clock) “tm_ltck”.
The general operation of a memory device will be described in detail with reference to FIG. 1.
FIG. 1 is a timing diagram showing activation and precharge of a memory device (for example, SDRAM) when it properly operates.
Referring to FIG. 1. CLK is an external clock signal. tCLK refers to a cycle of CLK. CMD refers to a command signal. ACT refers to an activation command, while PCG refers to a precharge command. tm_ltck is an abbreviation for test mode_long term clock, which refers to a test mode of a long-term clock signal. atvp is an abbreviation for active pulse, which refers to a pulse signal generated in accordance with an ACT command to execute the activation command. pcgp stands for a precharge pulse which is a pulse signal generated in accordance with a PCG command to execute the precharge command.
As shown in FIG. 1, when tm_ltck is at a low level, i.e., when the test mode using a long-term clock is disabled, the memory device generates an atvp signal for activating the memory device in response to an ACT command signal and a pcgp signal for precharging the memory device in response to a PCG command signal. As explained above, however, when a burn-in system driving at a low frequency is used, a high frequency memory device should be tested in a test mode of a long-term clock signal.
FIG. 2 is a timing diagram showing activation and precharge in the test mode of a long-term clock signal.
As shown in FIG. 2, CLK outputted from a burn-in system operating at a low frequency is used in a test mode where tm_ltck is at a high level.
When an ACT command is applied at the rising edge of a long-term clock signal (long tCK), the memory device generates an atvp signal for performing low activation.
Subsequently, the memory device automatically generates a pcgp signal at the falling edge of the long-term clock signal to perform a precharge operation.
A high-level activation of tm_ltck will be explained in detail with reference to FIG. 2.
When an activation command is applied at the rising edge of an external clock signal 1, an atvp signal within the memory device is activated to perform low activation. After lapse of the time period tRAS, a pcgp signal within the memory device is activated to automatically perform precharge at the falling edge of the external clock signal 1. Accordingly, another activation command can be applied at the rising edge of an external clock signal 2. In other words, it is possible to perform a burn-in test on a memory device using a system operating at a low frequency within a reduced testing time.
A low-level activation of tm_ltck will now be explained.
When an activation command is applied at the rising edge of the external clock signal 1, an atvp signal within the memory device is activated to perform low activation. After lapse of the time period tRAS, a precharge command is applied at the rising edge of the external clock signal 2 to activate a pcgp signal within the memory device and perform precharge. Subsequently, another command, for example, an activation command, is applied at the rising edge of an external clock signal 3. It is required to reduce tCK to minimize tRAS while testing the memory device using a system operating at a low frequency. In this case, the overall testing time cannot be reduced.
As shown in FIG. 2, when a long-term clock signal is applied to test a memory device, it is synchronized with the falling edge of an external clock signal to automatically perform a precharge operation, without applying a separate precharge command.
However, such an automatic precharge may cause problems as shown in FIG. 3.
FIG. 3 is a timing diagram showing activation and precharge operations in the test mode of a long-term clock signal in the prior art. According to the prior art, even when a precharge is not required, a long-term clock signal is synchronized with the falling edge of an external clock signal to automatically perform precharge.
Since a precharge is automatically performed at the falling edge of the external clock CLK even in an operation which does not require a precharge, such as an MRS (mode register set) or EMRS (extended mode register set) operation, after entry into the tm_ltck test mode (i.e., tm_ltck=high level), there is a likelihood of improper operation or unstable test mode operation, which will lower the reliability of the test results.